How to Pass Command-Line Variables to GNU Makefiles

Introduction

GNU Make is an essential tool for automating build processes in software development. One of its powerful features is the ability to use variables, which can be dynamically assigned values from various sources, including command-line arguments. This tutorial will guide you through different methods of passing additional variables to GNU Makefiles using command-line inputs.

Understanding Variables in Makefiles

In a Makefile, variables act as placeholders for data that can change based on the build context or environment. Variables help create flexible and reusable Makefile rules. There are several ways to set these variables:

Environment Variables: These are variables from your shell environment.
Command-Line Arguments: Passed directly when invoking make.
Makefile Assignments: Defined within the Makefile itself.

The scope of a variable can differ based on how it’s defined or passed, affecting its accessibility across targets and sub-make invocations.

Passing Variables via Command Line

One straightforward way to pass variables is through command-line arguments when invoking make. This method allows you to override any existing definitions in the Makefile.

Basic Syntax

To set a variable from the command line:

make <target> VAR=value

For example, if your Makefile contains a target that uses $(VAR), running:

make action VAR=something

will pass something as the value for VAR.

Command-Line Arguments vs. Environment Variables

Command-line arguments take precedence over variables defined in the environment.
If you use both methods, command-line settings will override those from the environment.

Example:

MESSAGE1=YES MESSAGE2=NG make send MESSAGE2=OK

Output:

echo YES OK
YES OK

In this example, MESSAGE2 is set to NG in the environment but overridden by OK on the command line.

Propagation to Sub-makes

Command-line variables do not propagate automatically to sub-make invocations. To pass variables to a sub-make, you must explicitly define them:

make target VARIABLE=value

For more complex scenarios involving multiple levels of Makefiles, consider using the --define option or exporting variables within the parent Makefile:

export VARIABLE=value
$(MAKE) -C target

This ensures that sub-make invocations inherit these settings.

Best Practices

Naming Conventions: Use uppercase for environment and command-line variables to differentiate them from local Makefile variables.
Default Values: Define default values in your Makefile using conditional assignment (?=):
```
VAR ?= default_value
```
This ensures that VAR has a value even if it is not set via the environment or command line.
Documentation: Document any variables you expect to be passed from the command line within your Makefile for clarity and ease of use by others.

Example

Consider a simple Makefile:

action:
    @echo Argument is $(argument)

To execute with a specific argument, run:

make action argument=something